1. Field of the Invention
The present invention relates to the utilization of read/writable memory located in a semiconductor chip with a microprocessor which can be read from and written to prior to the completion of a computer system's power-on, self-test program(POST). More particularly, it relates to the use of the read/writable memory for hardware interrupt routine testing.
2. Description of the Related Art
When a computer system is turned on, it typically implements a POST program to verify the functionality of its components. Conventionally, it has been assumed that prior to the verification of a computer system's main random access memory(RAM), no reliable read/writable memory is available to the system other than a component microprocessor's few internal registers. As a result of the perceived lack of reliable read/writable memory, hardware interrupt routines have been difficult to test.
When a failure occurs in the testing of hardware interrupt routines (or any other POST testing), the POST should identify as precisely as possible which component has failed. Precise component failure identification is beneficial because it results in more cost-effective effective and efficient repairs. Illustratively, when using the POST, a failure often can only be isolated to several suspect components. To repair this failure requires either 1) replacing all the suspect components; or 2) conducting additional testing to determine which of the suspect components is faulty and replacing it. The amount of additional testing and/or replacement of components required is dependent upon the number of suspect components. Consequently, more precise tests result in fewer suspect components and more cost-effective and efficient repairs.
To accomplish precise fault identification, the POST should ideally be performed in a "crawl out" sequence, that is, a component must first be tested before it is used to test other components. This methodology yields a chronological hierarchy of testing, starting with the most fundamental components and building through more complex ad dependent ones. A consequence of the "crawl out" sequence is the necessary assumption that the bare minimum components needed to implement the POST, which is stored in read-only memory(ROM), are functional. These components include the microprocessor, the ROM, and the components necessary for the microprocessor to read the ROM.
Reliable read/writable memory is memory whose functionality has been verified pursuant to the "crawl out" sequence. The major and often the only source of read/writable memory available to a computer system is the main RAM. A problem arises in that the main RAM is dependent on many other components, and therefor should be tested late in the "crawl out" sequence. Because the main RAM must be regarded as unreliable until tested, no read/writable memory has been though to be reliable prior to the verification of the main RAM except for the microprocessor's few internal registers.
This lack of reliable read/writable memory has made testing of hardware interrupt routines difficult. Hardware interrupts are the communication pathways between the microprocessor and different hardware devices and components thereof. In a typical personal computer (PC) architecture which may utilize, for example, an Am386 microprocessor, interrupts are handled in the following fashion. A device connects to a chained pair of programmable interrupt controllers(PIC) via one of fifteen interrupt request lines(IRQs). When a device needs servicing, it initiates an interrupt by sending a signal on the appropriate IRQ line. The signal is received by the PIC and converted into an eight bit interrupt number which identifies the IRQ line. The PIC, in turn, is connected to the microprocessor and sends it the eight bit interrupt number. Upon receipt of the interrupt number, the microprocessor 1) stores the information necessary to return to the job from which it is interrupted and 2) converts the interrupt number into an interrupt vector table address for that particular device. The vector table address specifies a location in an interrupt vector table where a physical, interrupt handler address may be found. The interrupt vector table may be located in either the system ROM or RAM, but as described below, RAM is ordinarily preferable.
The computer program located at the physical handler address is the interrupt service routine which is used to service an interrupt. In this manner, the microprocessor has used the interrupt vector table to translate an interrupt number into the physical address of an interrupt service routine.
Many devices are capable of generating a number of different types of interrupts on the same IRQ line. In a diagnostic environment each type of interrupt will require its own interrupt service routine and therefore its own interrupt vector. The result is that the interrupt vector table changes for each different type of interrupt. The interrupt vector table is therefore ordinarily set in RAM where such changes may be readily made. The microprocessor then implements whichever interrupt service routine is located at the physical address it reads from the interrupt vector table. The interrupt service routine services the interrupt and, upon completion, the microprocessor reloads the job information and returns to processing the interrupted job.
In testing the interrupts during POST, a problem arises in that the interrupt vector table may be very large to accommodate the multiplicity of different types of interrupts. The table needs frequent updating and modification. However, as indicated earlier, main RAM cannot be tested early in the POST and therefore cannot be regarded as reliable at that point in POST when interrupt testing is to be done. One non-optimal solution to the problem is to reproduce in ROM all of the different permutations of the interrupt vector tables required by the multiplicity of different types of interrupts. This is an extremely space inefficient solution that could require a large amount of valuable ROM space. Consequently, to perform a proper "crawl out" sequence, testing of the hardware interrupts should be completed before that of the main RAM. As a result, it has been conventionally assumed that no reliable read/writable memory was available to store the interrupt vector table for hardware interrupt testing. Therefore, hardware interrupt testing was not implemented without either relying on the untested main RAM, or using large amounts of ROM to store the interrupt vector table. The technique of using the untested main RAM is unsatisfactory because, if a fault is indicated, it is not discernable as to whether the fault is in the RAM or in the interrupt hardware. The technique of using ROM for storing the interrupt vector table yields a more precise fault identification. However, ROM is not readily modifiable and therefore large amounts of ROM must be used to store the multiple interrupt vector tables required to service multiple component devices.